1. Field of the Invention
The present invention relates to a semiconductor device having thin film transistors (hereinafter, referred to as TFTs) formed on an insulating surface of glass, plastics, or the like. In particular, included in the semiconductor devices are pulse output circuits such as a shift register circuit, latch circuit, buffer circuit, and level shift circuit, and amplification circuits such as an amplifier, each being used as a driver circuit of a display device.
2. Description of the Related Art
In recent years, a display device having a semiconductor thin film formed on an insulator such as a glass substrate, in particular, an electronic circuit manufactured with TFTs is used in various fields. The electronic circuit is often used in a display device. Active matrix display devices such as an LCD (liquid crystal display) are used in many products and widely spread. In the active matrix display device formed with TFTs, several hundred thousands to several millions of pixels are arranged in a matrix form, and a charge at each pixel is controlled by the TFT disposed at each pixel to thereby display an image.
As a further updated technique, a polysilicon TFT technique is being developed in which on the substrate a driver circuit is formed in a peripheral region of a pixel portion by using TFTs simultaneously with the pixel portion including pixel TFTs which constitute pixels. This greatly contributes to reduction in size and lowering of power consumption of the device, and accordingly such a display device is becoming indispensable to a display unit and the like provided in a mobile information terminal whose application field is notably widened in recent years.
Incidentally, in recent years, the display device is adopted in a display unit of various electronic equipments, and its industrial field is steadily expanding. Recently, it has been actively adopted in relatively inexpensive electronic equipments, and further reduction in costs is thus desired.
In general, in a semiconductor device, a CMOS circuit is adopted in which both n-channel TFTs and p-channel TFTs are used in combination. A display device has a multilayer structure with manufacturing steps of: film formation; exposure with photomasks; and etching are repeated. The steps are extremely complicated, and manufacturing costs thus increase. In addition, in a case of integrally forming the driver circuit and the pixel portion on the substrate as described above, yield is intensely affected by the steps since the defect of a part leads to the defect of a product as a whole.
A method of reducing manufacturing costs comprises reducing the number of steps as much as possible and manufacturing a device in a simple way as well as in a short period of time. Here, a display device is manufactured not with the CMOS structure but with a structure with TFTs of a single polarity in which either n-channel TFTs or p-channel TFTs are used, as a driver circuit structure. Thus, the number of steps of doping an impurity which imparts a conductivity type to semiconductor layers can be mathematically reduced to half, and further, the number of photomasks can also be reduced, which is effective to a great extent. Moreover, the manufacturing steps become simpler with a contribution to an improvement of yield.
FIG. 2 shows an example of an inverter formed of two n-channel TFTs. The inverter is of a dual input type in which signals are inputted to gate electrodes of TFTs 201 and 202, and an inverted signal of an input signal of one TFT is the input of the other TFT.
An operation of the inverter shown in FIG. 2 is now simply explained. It should be noted that in this specification, on explaining a structure and operation of a circuit, different names are appropriately given to three electrodes of a TFT, that is, xe2x80x9cgate electrode, input electrode, and output electrodexe2x80x9d or xe2x80x9cgate electrode, source region, and drain regionxe2x80x9d. When the operation of the TFT is explained, a gate-source voltage is considered in many cases. However, it is difficult to make a rigid distinction between the source region and the drain region of the TFT due to its structure. If unified names are given thereto, confusion may be caused on contrary. That is the reason why the different names are used here. When the input/output of a signal is explained, the electrodes are referred to as input electrode and output electrode. When the gate-source voltage or the like of the TFT is explained, one of the input electrode and the output electrode is referred to as source region, and the other as drain region.
Further, xe2x80x9ca TFT is ONxe2x80x9d means a state in which the absolute value of the gate-source voltage of the TFT exceeds a threshold voltage with a current flowing between the source and the drain. On the other hand, xe2x80x9ca TFT is OFFxe2x80x9d means a state in which the absolute value of the gate-source voltage of the TFT does not reach a threshold voltage with no current flowing between the source and the drain. As to the threshold value, for the sake of simple explanation, it is assumed that there is no fluctuation in respective TFTs. Threshold values of n-channel TFTs are uniformly set to VthN, and threshold values of p-channel TFTs are uniformly set to VthP.
First, when H level is inputted to an input terminal (In) and L level is inputted to an inverted input terminal (Inb), the TFT 201 is turned OFF and the TFT 202 is turned ON. Then, L level appears at an output terminal (Out) and its voltage becomes VSS. On the other hand, when L level is inputted to the input terminal (In) and H level is inputted to the inverted input terminal (Inb), the TFT 201 is turned ON and the TFT 202 is turned OFF. Then, H level appears at the output terminal (Out).
At this time, a potential at the time when the output terminal (Out) becomes H level is considered.
In FIG. 2, when H level is inputted to the gate electrode of the TFT 201, L level is inputted to the gate electrode of the TFT 202. Then, the TFT 201 is turned ON, the TFT 202 is turned OFF, and thus, the potential of the output terminal (Out) begins to increase. When the potential of the output terminal (Out) reaches (VDDxe2x88x92VthN), the gate-source voltage of the TFT 201 becomes equal to the threshold value VthN. That is, at this moment, the TFT 201 is turned OFF so that the potential of the output terminal (Out) cannot increase any further.
A case is considered in which inverters are connected in a plurality of stages, as shown in FIG. 12A. Among the inverters of FIG. 12A, only an initial inverter (InvA) is of such a single input and single output type as shown in FIG. 12B. Each of subsequent inverters (InvB) is of such a dual input and single output type as shown in FIG. 12C in order to suppress a shoot-through current at the time of the circuit operation as much as possible. It should be noted here that a gate electrode of a TFT 1201 is connected to a high potential side power supply VDD and remains in an ON state as long as the gate-source voltage of the TFT 1201 becomes lower than the threshold value. Therefore, even when a TFT 1202 is turned ON, it is possible to obtain L level output by setting a current ability of the TFT 1202 larger than that of the TFT 1201, though the output does not become completely equal to VSS.
In such a case, even when an amplitude of the input signal is in a range of VDD to VSS, the amplitude may be attenuated after passing through the stages of inverters one after another due to an influence of the threshold values of the TFTs 1201 and 1211, as shown in FIG. 12D.
The present invention has been made in view of the above, and an object of the present invention is therefore to provide a circuit which is formed of TFTs of a single polarity and which is capable of operating without causing such amplitude attenuation of an output signal as described above.
To solve the above problems, the present invention employs the following measures.
In an inverter shown in FIG. 2, the cause of generation of output amplitude attenuation is as follows. That is, when L level is inputted to an input terminal (In) and H level is inputted to an inverted input terminal (Inb), a potential applied to a gate electrode of a TFT 201 is equal to a potential on the input electrode side of the TFT 201, that is, a high potential side power supply VDD. Therefore, a potential of an output terminal (Out) is only allowed to increase up to (VDDxe2x88x92VthN).
In other words, when H level appears at the output terminal (Out), in order to obtain a state in which its potential is equal to VDD, the potential applied to the gate electrode of the TFT 201 needs to be higher than VDD, or to be precise, higher than (VDD+VthN).
Therefore, in the present invention, to solve the above problems, a capacitor means is employed to store a charge equivalent to a threshold voltage of the TFT 201 in advance. When a signal is inputted thereto, the charge thus stored is added to the input signal, whereby the potential applied to the gate electrode of the TFT 201 is raised to (VDD+VthN).
According to the present invention, there is provided a semiconductor device comprising first to fourth transistors and a capacitor means, characterized in that:
the first to fourth transistors each have the same conductivity type;
a first electrode of the capacitor means is electrically connected to a first signal input terminal, and a second electrode of the capacitor means is electrically connected to a gate electrode of the first transistor;
a gate electrode of the second transistor is electrically connected to a second signal input terminal;
an input electrode of the first transistor is electrically connected to a first power supply, and an output electrode of the first transistor is electrically connected to a signal output terminal;
an input electrode of the second transistor is electrically connected to a second power supply, and an output electrode of the second transistor is electrically connected to the signal output terminal;
a gate electrode and an output electrode of the third transistor each are electrically connected to the signal output terminal, and an input electrode of the third transistor is electrically connected to the second electrode of the capacitor means; and
a gate electrode and an output electrode of the fourth transistor each are electrically connected to the second electrode of the capacitor means, and an input electrode of the fourth transistor is electrically connected to the first electrode of the capacitor means.
In addition, according to the present invention, there is provided a semiconductor device comprising first to fourth transistors and a capacitor means, characterized in that:
the first to fourth transistors each have the same conductivity type;
a first electrode of the capacitor means is electrically connected to a first signal input terminal, and a second electrode of the capacitor means is electrically connected to a gate electrode of the first transistor;
a gate electrode of the second transistor is electrically connected to a second signal input terminal;
an input electrode of the first transistor is electrically connected to a first power supply, and an output electrode of the first transistor is electrically connected to a signal output terminal;
an input electrode of the second transistor is electrically connected to a second power supply, and an output electrode of the second transistor is electrically connected to the signal output terminal;
a gate electrode and an output electrode of the third transistor each are electrically connected to the signal output terminal, and an input electrode of the third transistor is electrically connected to the second electrode of the capacitor means; and
a gate electrode of the fourth transistor is electrically connected to the second electrode of the capacitor means, an input electrode of the fourth transistor is electrically connected to the first electrode of the capacitor means, and an output electrode of the fourth transistor is electrically connected to the signal output terminal.
According to the present invention, the capacitor means is a capacitor means storing a threshold voltage of the fourth transistor, and it is characterized in that the stored voltage is added to a potential of a signal inputted from the first signal input terminal, and the thus obtained potential is applied to the gate electrode of the first transistor. With this structure, a gate-source voltage of the first transistor is at least the threshold value all the time, making it possible to obtain the output without causing the amplitude attenuation.
Further, according to the present invention, it is characterized in that the semiconductor device is consist of transistors of a single polarity, i.e., consist of only n-channel transistors or only p-channel transistors. With this structure, it is possible to simplify manufacturing steps of a display device.
In a display device of the present invention, the capacitor means may be formed of a capacitance between the gate electrode and the input electrode of the fourth transistor, or formed of two materials selected from the group consisting of an active layer material, a material for forming a gate electrode, and a wiring material, and an insulating layer between the two materials.
In the display device of the present invention, it is characterized in that a signal inputted to the second signal input terminal is obtained by inverting the polarity of a signal inputted to the first signal input terminal. With this structure, when a signal appearing at the output terminal is either H level or L level, no shoot-through current is generated between a power supply VDD and a power supply VSS in a circuit, making it possible to reduce the consumption current.